#include "bsp/bsp.h"
#include "adc.h"
#include "tim.h"
#include "spi.h"
#include "gpio.h"
#include "version.h"


void SystemClock_Config(void)
{

  	RCC_OscInitTypeDef RCC_OscInitStruct;
  	RCC_ClkInitTypeDef RCC_ClkInitStruct;

    /**Configure the main internal regulator output voltage 
    */
  	__HAL_RCC_PWR_CLK_ENABLE();

  	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

    /**Initializes the CPU, AHB and APB busses clocks 
    */
	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
	RCC_OscInitStruct.HSEState = RCC_HSE_ON;
	RCC_OscInitStruct.LSIState = RCC_LSI_ON;
	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
	RCC_OscInitStruct.PLL.PLLM = 4;
	RCC_OscInitStruct.PLL.PLLN = 168;
	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
	RCC_OscInitStruct.PLL.PLLQ = 7;

  	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  	{
  	}

    /**Initializes the CPU, AHB and APB busses clocks 
    */
	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
									|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;


  	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
  	{
  	}

    /**Configure the Systick interrupt time 
    */
  	HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);

    /**Configure the Systick 
    */
  	HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);

  	/* SysTick_IRQn interrupt configuration */
  	HAL_NVIC_SetPriority(SysTick_IRQn, SYSTICK_IRQ_PRIOTIRY, 0);
}

void HAL_MspInit(void)
{
	__HAL_RCC_SYSCFG_CLK_ENABLE();
  	__HAL_RCC_PWR_CLK_ENABLE();

  	HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  	/* SysTick_IRQn interrupt configuration */
  	HAL_NVIC_SetPriority(SysTick_IRQn, SCHED_TIMER_IRQ_PRIORITY, 0);
}

void MX_DMA_Init(void) 
{
	/* DMA controller clock enable */
	__HAL_RCC_DMA1_CLK_ENABLE();
	__HAL_RCC_DMA2_CLK_ENABLE();
  	/* DMA interrupt init */
  	/* DMA1_Stream0_IRQn interrupt configuration */
  	HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 4, 0); // SPI RX - must have lower priority than SPI TX
                                                 // and higher priority than the control loop handler
  	HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);

  	/* DMA1_Stream7_IRQn interrupt configuration */
  	HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 3, 0); // SPI TX - must have higher priority than SPI RX
                                                 // and higher priority than the control loop handler
  	HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);

}

void MX_IWDG_Init(void)
{
#if (CONFIG_DEBUG==0)
	IWDG_HandleTypeDef hiwdg;
	//wdog clk is 32k, 2s timeout
  	hiwdg.Instance = IWDG;
 	hiwdg.Init.Prescaler = IWDG_PRESCALER_16;
  	hiwdg.Init.Reload = 4095;
	HAL_IWDG_Init(&hiwdg);
#endif
}

void wdog_reload(void) {
#if (CONFIG_DEBUG==0)
	IWDG_HandleTypeDef hiwdg;
	hiwdg.Instance = IWDG;
	HAL_IWDG_Refresh(&hiwdg);
#endif
}

u8 mcu_chip_id(u8 *buff)
{
	u32 values[] = { REG32(0x1FFF7A10), REG32(0x1FFF7A14), REG32(0x1FFF7A18)};
	memcpy(buff, values, sizeof(values));
	return sizeof(values);
}

